IC Delayer
Remove the multi-layer structure of the chip (passivation, metal, Oxide) by repetitive combination of different approaches (ion etching/ chemical etching/ mechanical polishing), to enable clearly presenting circuit layout structure of each layer for later experiments.
What we can do
Reverse analysis by delayering each metal layer with wet/dry etching and polishing, zoom in with optical microscope (50x ~ 1500x) or electron microscope (still greater magnification) to identify metal leakage or burn out, metal short among other errors, run VC control reference with electron microscope to determine generation of secondary electrons.
Reverse Engineering Analysis
- Ordinary Cu, Al metallic layer delayer (Cratering, Via, ARC, Metal, Barrier metal, Substrate…)
- Gate oxide pin hole (together with SEM scanning)
- FinFET process
SEM (HITACHI SU8220 )
- Smaller process or micro error inspection
- Secondary electron scanning
- 3D substrate review over FinFET process
EDS element analysis assessment
The Superiority of LF
The Superiority of LF
- Market leading analysis capacity: Up to 10nm Cu process delayer technique
- Fast delivery: Urgent demand completed within 1 working day
- Provide high resolution of surface structure image in the industry and fast material analysis along with HR-SEM & EDS
Case Sharing
Integrated solution of IC Delayer (1)
Integrated solution of IC Delayer (2)
FinFET process delayer
Integrated solution of IC Delayer (1)
IC delayer → OM reviewing → Contact layer scanning (VC) with SEM high and low voltage→ etching to gate oxide then view by SEM
Integrated solution of IC Delayer (2)
IC delayer to Contact → OM viewing and imaging →SEM electronic and secondary electronic scanning → polishing to poly → SEM scanning to get Poly Profile
FinFET process delayer
FinFET process delayer to Substrate → OM viewing and imaging →SEM scanning
Why Choose Lab First
EXPERTS team
Joint diagnostics Service
