FIB Circuit Edit/ CAD Probe Pad Debug
What we can do
♦ FIB circuit:
IC circuit edit is provided to the designers through FIB. Due to the merit of saving a photo mask redo, FIB significantly shortens time for IC prototype validation and time-to-market.
♦ CAD Probe Pad:
Using FIB, the points where signals must be measured are led to the surface of the IC so that a mechanical prober may retrieve internal signals in the IC.
♦ Backside FIB Circuit Edit:
Modifying a circuit from the backside is easier and has a higher success rate due to the limited flip-chip packaging substrate, advanced process continuously edging into 5nm, increasing metal winding layers, and more complex and compact circuits.
What is FIB?
The focus ion beam (FIB) technique may selectively etch (disconnect circuit) and deposit a conductor or a nonconductor (add a new circuit) by hitting sample surface with gallium ion along with organic gas.
The Superiority Of LF
- Minimum Operations On 5nm process metal With 3.5nm resolution.
- Maximum operations applicable To 8” wafers.
- Supports CAD Navigation.
- Precision laser guided stage.
- Built-In infrared microscope for observing CMP layer and isolating silicon layer.
- Two choices for metal wires: Tungsten (Low Resistance) or Platinum (Faster).
- Build with FEI DE/DX etching gas so as to increase the yield rate when apply to high aspect ratio and tighter circuit layout.
Model(17) | Capability | |
Process | Note | |
FEI V400ACE(4) | 14/20nm | l GDS Navigation l Backside FIB l W+PT+SiO2 dep. |
FEI 986-IET(2) | 28/40nm | l Sample size ≤ “8” Wafer & PCB l GDS Navigation l Backside FIB l W+SiO2 dep. |
FEI 986 (2) | 55/65nm | |
FEI V600CE/CE+(2) | 65/90nm | l GDS Navigation l W + SiO2 dep. l <“6” & PCB |
FEI V600(3) | ≥90nm | l GDS Navigation l PT/W dep. l <“6” & PCB |
FEI 200/800(4) | ≥0.13um | l PCB |
- Before FIB, test once more after decapsulation, wire bonding or packaging.
- Yield decreases if multiple modifications are made on the same IC.
- The resistance of conductor metal by FIB is higher than the original. If there are any requests for low resistance conductor, please specify it on the service order.
- Suggest providing GDSII circuit layout to facilitate navigation (partial area or layer will be fine), this can help increase the yield.
Case Sharing