IC Delayer

Remove the multi-layer structure of the chip (passivation, metal, IDL) by repetitive combination of different approaches (ion etching/ chemical etching/ mechanical polishing), to enable clearly presenting circuit layout structure of each layer for later experiments.

What we can do

Reverse analysis by delayering each metal layer with wet/dry etching and polishing, zoom in with optical microscope (50x ~ 1500x) or electron microscope (still greater magnification) to identify metal leakage or burn out, metal short among other errors, run VC control reference with electron microscope to determine generation of secondary electrons.

Reverse Engineering Analysis
  • Ordinary Cu, Al metallic layer delayer (Cratering, Via, ARC, Metal, Barrier metal, Substrate…)
  • Gate oxide pin hole (together with SEM scanning)
  • FinFET process
SEM (HITACHI SU8220 )
  • Smaller process or micro error inspection
  • Secondary electron scanning
  • 3D substrate review over FinFET process
EDS element analysis assessment
 

Case Sharing

Why Choose Lab First


EXPERTS team

Joint diagnostics Service

Perfect Advanced Equipment

LAB FIRST IS YOUR FIRST CHOICE

Ready to pursue your goal